Browse Prior Art Database

Implanted Emitter Process for Semiconductor Transistor

IP.com Disclosure Number: IPCOM000084624D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 102K

Publishing Venue

IBM

Related People

Barile, CA: AUTHOR [+3]

Abstract

There is a possibility of exposed unpassivated emitter-base (E-B) junctions during an implanted emitter process, because of SiO(2) undercutting below a Si(3)N(4) layer. This causes a lower Beta for the device than is acceptable.

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Implanted Emitter Process for Semiconductor Transistor

There is a possibility of exposed unpassivated emitter-base (E-B) junctions during an implanted emitter process, because of SiO(2) undercutting below a Si(3)N(4) layer. This causes a lower Beta for the device than is acceptable.

The problem is solved by opening all contacts to silicon using reactive ion etching. Alternatively, ammonium bifluoride, may be used to etch the oxide and nitride at approximately the same rate. This step eliminates the nitride overhang, which causes the unpassivated E-B junction.

Fig. 1 illustrates a semiconductor transistor device prior to the emitter formation. The structure includes a photoresist layer 4, base, emitter and collector contact areas 6, 8 and 10, respectively. Also shown are the contact holes 12 etched as stated above.

In Fig. 2, the N contact mask is exposed using AZ*1350H plus either benzoyl peroxide or LUPERSOL** 101. The resist is used as an implant mark.

In Fig. 3, arsenic 16 is then implanted in regions 8 and 10. Photoresist 4 is stripped by a low-temperature oxidation cycle (250-500 degrees C) for between 1/2 to 2 hours depending upon the temperature, followed by 9:1 sulfuric/nitric acid and at 100 degrees C for 30 minutes. Drive-in of the emitter proceeds as usual. * Trademark of Shipley Company, Inc. ** Trademark of Wallace & Tiernan Inc.; Lucidol Division

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