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Hybrid Associative Register Configuration

IP.com Disclosure Number: IPCOM000084645D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Hajek, SF: AUTHOR [+2]

Abstract

This translation buffer configuration for a virtual memory system maps a plurality of physical address entry blocks, with each block corresponding to a virtual address entry, into an array storage while leaving the virtual address entries in associative registers for easy parallel search access.

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Hybrid Associative Register Configuration

This translation buffer configuration for a virtual memory system maps a plurality of physical address entry blocks, with each block corresponding to a virtual address entry, into an array storage while leaving the virtual address entries in associative registers for easy parallel search access.

The logical address associated with a CPU request consists of a virtual address portion, comprising a segment field S(x) and a page field P(x), and a real address portion comprising a byte field B. The virtual address entries have (X-Y) bits as opposed to X bits in a conventional associative register configuration. A number of Y bits, equal to or less than P(x), is used as an index to an entry in a block of physical address entries in the array storage, the number being chosen in accordance with performance requirements.

Each entry in a block of entries contains a physical address value, a valid bit
(V) and a load bit (L). The valid bit is the page valid identification, while the load bit identifies that page which has been loaded after a table look-up.

At initial start-up all valid bits associated with the configuration are off. Therefore, when a CPU request is made, the virtual portion of the incoming logical address will not compare with any virtual entry in the associative registers. The absence of any compare signals the dynamic address translation (DAT) unit to perform a two-level table look-up operation, to translate the virtual portion of the logical address into a physical address. This may be accomplished in the conventional manner by using the segment field of the logical address as an index to an entry in a segment table, which contains a value representing the base address of a page table associated with the designated segment.

The page field of the logical address is then used as an index to an entry in the page table, which contains the physical address of the page and a valid bit indicating the page address is valid (0) or invalid (]). On most systems, a data request brings in a block of data. Therefore when the page table is accessed successive page (physical address) entries should be brought in and loaded as successive entries in the array storage.

The number of successive page table entries brought in is limited only by the number of available successive entries in the page table and the array storage space allocated to a virtual entry. Accordingly, the DAT unit brings in a page table entry and its valid bit identification, e.g., page entry A associated with virtual address X. During the write cycle, the virtual (X-Y) bits of the logical address are loaded into the virtual entry (0) with its valid bit set.

The DAT unit also provides an address value for the arrav storage block corresponding to the virtual entry which is concatenated with the Y bits that are used as a...