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Plural Address Lengths in a Computer System

IP.com Disclosure Number: IPCOM000084661D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Brooke, KE: AUTHOR

Abstract

A computer can be made with an address control which controls two different address sizes. A program can then be written with instructions using one of two different size address fields, such as 24 or 32-bit address fields, which may contain virtual addresses.

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Plural Address Lengths in a Computer System

A computer can be made with an address control which controls two different address sizes. A program can then be written with instructions using one of two different size address fields, such as 24 or 32-bit address fields, which may contain virtual addresses.

The address control provides an extra bit position in the storage key for each storage block in the real memory of the type used in IBM S/370 computer systems. When the extra bit is zero (0), an instruction fetched from that storage block would access storage with 24-bit addresses. When the bit is one (1), an instruction fetched from that storage block would access storage with 32-bit addresses. Thus, at the time an instruction is fetched, the address size for an operand in the instruction is determined by the address size bit in the storage key for the storage block containing that instruction.

Consequently, the intermixed execution of 24-bit and 32-bit virtual addresses is obtained by sensing the settings of the address size bit in each storage key for each block accessed by a program. Existing programs may be restricted to blocks having only instructions of one size, e.g. 24 bits. Intermixed execution can be supported by a branch and a move character instruction which always executes with 32-bit addressing. This instruction is usable by a program residing in a 24-bit address block to access directly a program or data residing in a block located at a logical add...