Browse Prior Art Database

Instruction Set Extension

IP.com Disclosure Number: IPCOM000084669D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Bains, RL: AUTHOR [+4]

Abstract

Instruction sets are extended by detecting the nonexecutable instructions (invalid op code) and trapping to a mechanism, user-supplied logic or predefined routines, for executing the otherwise nonexecutable instructions.

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Instruction Set Extension

Instruction sets are extended by detecting the nonexecutable instructions (invalid op code) and trapping to a mechanism, user-supplied logic or predefined routines, for executing the otherwise nonexecutable instructions.

One implementation for a soft op code computer system is schematically shown in Fig. 1. Upon detecting an invalid (soft) op code, the value in op code register 10 is transferred into the low-order bit positions of shift register 15. The high-order bit positions of register 15 are forced to zero during this transfer and register 15 is shifted one bit left whereby an address is formed therein for accessing a table of addresses in storage 25.

The address formed in register 15 is transferred to storage address register (SAR) 20 for accessing the table in storage 25. The address read out from storage 25 is entered into storage data register (SDR) 30 and is transferred therefrom into instruction address register (IAR) 35, after its contents have been transferred to address recall register (ARR) 40 to preserve the return address.

The address in IAR 35 functions as a branch to the mechanism (routine) for executing the otherwise invalid instruction. The table in storage 25 also contains address for branching to routines for handling truly invalid op codes. A flow diagram illustrating the operation is contained in Fig. 2.

Another implementation for handling soft or user-defined op codes is shown in Fig. 3. In this arrangement the...