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Browse Prior Art Database

Retry Circuit for Array Memory

IP.com Disclosure Number: IPCOM000084691D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Hackett, RS: AUTHOR

Abstract

This system is a method/apparatus for addressing around a prospective single-failure address in a random-access, word-organized memory, especially those memories formed from a technology prone to intermittent failure.

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Retry Circuit for Array Memory

This system is a method/apparatus for addressing around a prospective single-failure address in a random-access, word-organized memory, especially those memories formed from a technology prone to intermittent failure.

The method comprises the steps of detecting a parity error, upon reading the contents of the ith memory address, loading the address into a holding address register which cannot be reset, and reloading the proper memory contents into the ith address and a buffer. When the contents of the memory and holding address registers are equal, then data is accessed from the buffer instead of the memory location, the holding and buffer registers being dedicated to this ith address until a parity error is detected at another address.

When a parity check is detected on the storage data register (SDR), the storage address register (SAR) is loaded into the back-up storage address register (BSAR) which cannot be reset. The machine will then have to initiate a checkpoint restart which would load the array again. When the failing address is encountered, the data will be loaded into the SDR normally; but, due to the comparator equal signal, it will also be loaded into the back-up storage data register (BSDR). This is the only mechanism to change the BSDR.

When the array encounters the failing address again, it will (due to the comparator equal signal) cause the data to be taken from the BSDR instead of the SDR. In this manner, every tim...