Browse Prior Art Database

Verifying Operation of Computer Register

IP.com Disclosure Number: IPCOM000084700D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Curlander, PJ: AUTHOR [+2]

Abstract

This description relates to a method for verifying the operation of the control portion of a multibit data register having at least one parity bit position. The method utilizes at least one stage of an independently clockable shift register, which shift register contents are added for the purpose of generating a group even parity when any control line regulating the writing of information into the register fails.

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Verifying Operation of Computer Register

This description relates to a method for verifying the operation of the control portion of a multibit data register having at least one parity bit position. The method utilizes at least one stage of an independently clockable shift register, which shift register contents are added for the purpose of generating a group even parity when any control line regulating the writing of information into the register fails.

Relatedly, the method is seen as comprising the steps of toggling the shift register each time the associated data register is loaded, modifying the data register parity by logically combining (exclusive ORing) the parity with the previous value of the shift register, and checking the (odd) parity condition of the overall parity of the shift register and data register.

Referring to the figure, there is shown a byte register (8 bit positions) with a ninth position reserved for parity. Ordinarily, the parity bit is odd and in the absence of any failure when data is transferred out, there will be odd parity out. It is observed that the parity bit is exclusive ORed on the input side with the output of the reentrant shift register, and is exclusive ORed with the output of the first register stage on the output side. The two-stage shift registers simply perform a toggle function each time the data register is loaded.

The toggle controls must be independent, that is, up to the next level of checking of the data and parit...