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Error Correction System

IP.com Disclosure Number: IPCOM000084701D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Mason, GG: AUTHOR

Abstract

An error correction system is shown in which six parity check bits are generated over the data bits when data is written into storage according to the following equations: C1 = 1V2V 3V 4V 6V13V15V16 C2 = 2V3V 4V 5V 6V 7V 8V 9 C3 = 6V7V 8V 9V10V11V12V13 C4 = 2V9V11V12V13V14V15V16 C5 = 1V3V 5V 7V10V12V14V16 C6 = 1V4V 5V 8V10V11V14V15.

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Error Correction System

An error correction system is shown in which six parity check bits are generated over the data bits when data is written into storage according to the following equations: C1 = 1V2V 3V 4V 6V13V15V16 C2 = 2V3V 4V 5V 6V 7V 8V 9 C3 = 6V7V 8V 9V10V11V12V13 C4 = 2V9V11V12V13V14V15V16 C5 = 1V3V 5V 7V10V12V14V16 C6 = 1V4V 5V 8V10V11V14V15.

These six parity check bits are written in parallel along with the data bits into storage. In later read cycles syndrome bits are generated according to the following equations: S1 = C1 V1V2V 3V 4- 6V13V15V16 S2 = C2 V2V3V 4V 5V 6V 7V 8V 9 S3 = C3 V6V7V 8V 9V10V11V12V13 S4 = C4 V2V9V11V12V13V14V15V16 S5 = C5 V1V3V 5V 7v10V12V14V16 S6 = C6 V1V4V 5V 8V10V11V14V15.

By the use of this error correction system, a single data bit error can be corrected during each read cycle. For example, if S1, S2 and S3 are each 1, any single error which occurs is in data bit 5. Correction for this bit is accomplished as in 1. If S1, S2 and S3 are active, the output line 2 from AND 1 becomes active, and is applied as one input to exclusive OR 4. Exclusive OR 4 then inverts data bit 5 on line 3 to generate corrected data bit 5. If on the other hand S1, S2 and S3 are not 1, and line 2 is not active and exclusive OR 4 does not invert data bit 5, then data bit 5 is correct as read. Each data bit is similarly corrected in parallel.

Single-bit errors may be discriminated from double-bit errors, as in II. Each syndrome is connected to exclusive OR 6 and OR 7. Output 8 of exclusive OR 6 (active when even) and output 10 of OR 7 are connected to AND 11. On a given read cycle, if an even number of syndrome bits are on, the ou...