Browse Prior Art Database

Phase Lock Using Variable Path Delay as Substitute for Frequency

IP.com Disclosure Number: IPCOM000084704D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Gindi, AM: AUTHOR

Abstract

In the prior art, phase-lock loops, as for example shown in USP 3,878,474, have utilized fractional frequency changes of a voltage-controlled oscillator (VCO) in order to provide slight adjustments of phase lead or lag, so as to maintain synchrony between a pair of signals. Relatedly, Furtney, USP 3,878,473 utilizes a variable time-delay element obtained from inserting a number in a counter counting down to zero, in order to provide the same relative phase adjustments in the time domain as the fractional cycle changes generated by a VCO in the frequency domain.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 2

Phase Lock Using Variable Path Delay as Substitute for Frequency

In the prior art, phase-lock loops, as for example shown in USP 3,878,474, have utilized fractional frequency changes of a voltage-controlled oscillator (VCO) in order to provide slight adjustments of phase lead or lag, so as to maintain synchrony between a pair of signals. Relatedly, Furtney, USP 3,878,473 utilizes a variable time-delay element obtained from inserting a number in a counter counting down to zero, in order to provide the same relative phase adjustments in the time domain as the fractional cycle changes generated by a VCO in the frequency domain.

The improvement uses a variable-path delay formed from at least a pair of paths of disparate electrical length and means for selecting the paths.

Referring to the figure, there is shown an apparatus 1 for synchronizing a first signal omega 1 on path 3 in phase and frequency to that of an input reference signal omega 2 on path 5. Relatedly, both the first and reference signals omega 1 and omega 2 are a submultiple of a master clock signal F(0) and in this embodiment are each of frequency F(0)/2/N/.

The apparatus comprises a phase detector 7 for generating a signal indicative of relative phase lag Q or lead between omega 2 and omega 1 applied thereto. In this embodiment, the phase detector 7 is in the form of a flip-flop from which the respective lag Q and lead Q signals are gated by AND gates 9 and 11, respectively, by the master clock or outp...