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Timing Circuit

IP.com Disclosure Number: IPCOM000084705D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Cummings, KD: AUTHOR

Abstract

A timing circuit is shown for producing a synchronized output from a master clock source. The master clock output is phase shifted into n signals phased 360/n degrees apart. Each signal gates one of a series of storage elements 10 arranged in a ring. Each element 10 is also gated by a START signal and each element degates the element preceding it by one phase. Thus, when the START signal occurs, one element will not be set and the following element will be set. The AND of the two conditions determines to within 360/n degrees which phased signal to gate to the using logic.

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Timing Circuit

A timing circuit is shown for producing a synchronized output from a master clock source. The master clock output is phase shifted into n signals phased 360/n degrees apart. Each signal gates one of a series of storage elements 10 arranged in a ring. Each element 10 is also gated by a START signal and each element degates the element preceding it by one phase. Thus, when the START signal occurs, one element will not be set and the following element will be set. The AND of the two conditions determines to within 360/n degrees which phased signal to gate to the using logic.

None of the logic is required to operate at a rate greater than the master clock frequency, and n is chosen so that the uncertainty is within the selected tolerance for synchronizing the external circuits. For example, a 40 MHz master clock source and six phases (n=6) produces a timing uncertainty of 4.2 nanoseconds at output terminal 20.

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