Browse Prior Art Database

Base Charge Reduction in Merged Transistor Logic Structures

IP.com Disclosure Number: IPCOM000084738D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Jaeger, RC: AUTHOR

Abstract

This description relates to a scheme for minimizing charge storage and current flow in the extrinsic base region of merged transistor logic structures.

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Base Charge Reduction in Merged Transistor Logic Structures

This description relates to a scheme for minimizing charge storage and current flow in the extrinsic base region of merged transistor logic structures.

In high-performance merged transistor logic (MTL) structures and bipolar transistor structures, stored charge in the extrinsic base region limits the intrinsic device speed limit by being the dominant contributor to the collector time constant Tc, and accounting for as much as one half of the emitter time constant Te. A technique for significantly reducing the stored base charge and minimizing the Gummel number of the intrinsic base region (thus maximizing upward beta) is described below.

The charge stored in the extrinsic base region may be minimized by doping the base heavily, since base charge Qb is inversely proportional to the impurity concentration Na. However, the collector current depends upon the total number of impurities in the intrinsic base region (the Gummel number), and a large Na dx reduces this current. To minimize the base charge but maintain the collector current level, a two-step implantation technique is proposed for the base region.

The base region will be defined as shown in Fig. 1. In the first step, only the extrinsic base region and MTL injector will be formed. The future collector sites will remain masked, and the extrinsic base is implanted with a relatively heavy dose. The collector site masks are then stripped, and the total...