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Method for Designing Efficient Connector Patterns for Mounting Chips in LEM Technology

IP.com Disclosure Number: IPCOM000084739D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 47K

Publishing Venue

IBM

Related People

Lew, JS: AUTHOR

Abstract

In LEM (Liquid Encapsulated Module) technology, flat chips are designed with integrated circuitry just beneath one surface, and these chips are mounted in various configurations on a flat ceramic substrate. Mounting a chip on the substrate, and providing electrical connections between the two, are accomplished by numerous "pads" of "C4-joints". These pads are manufactured by flux soldering, their positions being chosen in advance; they are roughly cylindrical in shape, the middle being thicker than the ends.

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Method for Designing Efficient Connector Patterns for Mounting Chips in LEM Technology

In LEM (Liquid Encapsulated Module) technology, flat chips are designed with integrated circuitry just beneath one surface, and these chips are mounted in various configurations on a flat ceramic substrate. Mounting a chip on the substrate, and providing electrical connections between the two, are accomplished by numerous "pads" of "C4-joints". These pads are manufactured by flux soldering, their positions being chosen in advance; they are roughly cylindrical in shape, the middle being thicker than the ends.

A typical number of pads is 100 for a single chip. A typical pad diameter is
0.005 inch; a typical chip-substrate spacing is 0.003 inch; a typical chip is 0.1 inch square and 0.015 inch thick. Thus the geometrical configuration under a single chip may be visualized as two planes separated by a narrow gap and connected by many stubby right circular cylinders.

In operation, the two planes are oriented in a vertical direction, and the system is immersed in a chemically stable liquid. (The present liquid, called PPl, has a chemical composition C(6)F(14), low viscosity, specific gravity 1.7, boiling temperature 57 degrees C., and surface tension 12.0 dyne/cm at 25 degrees C.) During operation, electric current flows in the system circuits, heat is generated in chip and substrate, the liquid temperature is raised nearly to boiling, and vapor bubbles are formed as a result. These bubbles grow, merge, and rise.

Often the planned gap between adjacent pads does not permit the passage of free vapor bubbles, whence the region enclosed by these pads accumulates a number of such bubbles, and these small trapped bubbles merge into a single large bubble. Continued operation of the system produces further expansion of this large bubble. Portions of this trapped bubble squeeze out between the pads, break off into small bubbles, and float upwards to the liquid surface. The large bubble thus undergoes rapid volume oscillations, and this physical phenomenon poses several manufacturing problems.

1. The successive escape of vapor bubbles is the principal cooling mechanism for the system. If the escape process is hindered, then the cooling rate is decreased, and the admissible current is restricted, whence the operating speed is limited.

2. Temperature increases in chip and substrate produce thermal expansion at different rates, and this unequal expansion of the two planes creates shear forces in the connecting pads. Eventually these effects generate pad cracking, and thus decrease the system lifetime.

3. Impurities accumulate in the operating liquid and deposit near the oscillating bubble boundaries. These deposits may permit conduction, or produce corrosion, and thus decrease the system lifetime. Such deposits do not occur when free bubbles can easily escape.

4. The large trapped bubble, through its presence and oscillation, exerts periodic forces on the chip and...