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Browse Prior Art Database

Complimentary Recessed Oxide MOS FET Circuit Structure

IP.com Disclosure Number: IPCOM000084745D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR

Abstract

Described is a process for producing a complimentary recessed oxide type metal-oxide semiconductor (MOS) integrated circuit structure. Referring to the drawings, Figs. 1 through 5, the method comprises providing a monocrystalline silicon wafer or substrate, depositing a boron doped oxide 1, delineating the desired pattern thereon for the deposition of an arsenic, phosphorous, or any other desired doped oxide 2, and drive-in of the diffusion to produce a configuration as shown at 3 in Fig. 1.

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Complimentary Recessed Oxide MOS FET Circuit Structure

Described is a process for producing a complimentary recessed oxide type metal-oxide semiconductor (MOS) integrated circuit structure. Referring to the drawings, Figs. 1 through 5, the method comprises providing a monocrystalline silicon wafer or substrate, depositing a boron doped oxide 1, delineating the desired pattern thereon for the deposition of an arsenic, phosphorous, or any other desired doped oxide 2, and drive-in of the diffusion to produce a configuration as shown at 3 in Fig. 1.

The surface of the semiconductor wafer is now completely stripped to a planar form by any suitable etching procedure and a gate oxide is grown as shown at 4 in Fig. 2, followed by a silicon nitride deposition at 5. A mask is provided to delineate a recessed channel pattern and the channels etched out to the desired depth and oxidized to form SiO(2) therein, as shown at 6.

The oxide formed on the nitride surface is removed and polysilicon deposited at the desired thickness, determined by conductivity requirements and the polysilicon delineated as shown at 7 in Fig. 3.

The silicon nitride layer is etched and an N+ doped oxide is grown to the desired pattern followed by a P+ doped oxide, as shown in Fig. 4. This is accomplished by an elevated temperature drive-in in the presence of HCl. This procedure is well known in the art. This procedure produces the junctions and gate oxide, as also shown in Fig. 4. The field-effect tra...