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Browse Prior Art Database

Structure and Process for FET High Density, Single Device Cell

IP.com Disclosure Number: IPCOM000084775D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Landler, PF: AUTHOR

Abstract

The structure described allows a one-device cell to share a single contact point to transfer the charge to be sensed to the bit sense (B/S) line. The process used to achieve this configuration uses Al(2)O(3) in the field and self-aligned poly-Si gate.

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Structure and Process for FET High Density, Single Device Cell

The structure described allows a one-device cell to share a single contact point to transfer the charge to be sensed to the bit sense (B/S) line. The process used to achieve this configuration uses Al(2)O(3) in the field and self-aligned poly-Si gate.

Fig. 1 is a top view of the above device where a diffused contact 1 between two gate areas 2 is shared by storage node 3 and storage node 4. The bit sense line 5 contacts the common contact 1. Word lines 6 and 11 form gates 2.

Fig. 2 is a cross section of the device which shows silicon substrate 7, over which is deposited a thin layer of silicon dioxide 8 and a layer of Al(2)O(3), 9, as well as a thicker layer of pyrolytic SiO(2), 10. These three layers are etched using conventt~nal photoli~hography masking techniques to open up for contact gates, 2 and storage nodes 3 and 4. Gate oxide 16 is then formed before polysilicon lines 11 are deposited to form the configuration, as shown, to make storage nodes 3 and 4 and gates 2. A layer of As or P doped oxide 12 is deposited and by conventional drive-in techniques, the N+ diffusions 13 and 14 are formed to complete the field-effect transistor (FET) source (drain) configuration as well as the drain (source) contact diffusion 15, which is contacted by suitable metallurgy such as aluminim and etched to form lines 4 and 5.

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