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Realtime Diagnosis (Probe Algorithm) using Single Pin Probe

IP.com Disclosure Number: IPCOM000084795D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 73K

Publishing Venue

IBM

Related People

Zobniw, LM: AUTHOR

Abstract

ABSTRACT: The cost to generate precalculating diagnostics using stuck (0, 1) fault simulation is increasing with logic complexity. This realtime diagnostic procedure does not require fault simulation and gives better diagnostic resolution than precalculated diagnostics. Probe Diagnostic Algorithm (PROBE) makes realtime deterministic decisions that direct single pin probe (probe) to as many probe nodes as are required, to diagnose a defect to the lowest repairable or replaceable unit. PROBE is applicable to other test systems, including multiple pin probe testers and manually positioned probes. PROBE is fully automatic or manually interactive.

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Realtime Diagnosis (Probe Algorithm) using Single Pin Probe

ABSTRACT: The cost to generate precalculating diagnostics using stuck (0,
1) fault simulation is increasing with logic complexity. This realtime diagnostic procedure does not require fault simulation and gives better diagnostic resolution than precalculated diagnostics. Probe Diagnostic Algorithm (PROBE) makes realtime deterministic decisions that direct single pin probe (probe) to as many probe nodes as are required, to diagnose a defect to the lowest repairable or replaceable unit. PROBE is applicable to other test systems, including multiple pin probe testers and manually positioned probes. PROBE is fully automatic or manually interactive.

Required Data: Physical Model describes the assembly (e.g., printed-circit card) consisting of interconnected subassemblies (modules) and nets. The assembly has a module and a probe side. Net includes all nodes that are physically interconnected and the interconnections. Nodes that affect the state of the net are called drivers. Nodes that are driven by the net are called sinks. Resistors on the net are called terminators. Nodes (tabs) that are accessible for all testing are called primary pins (PIO), which include primary outputs (PO) and primary inputs (PI). Nodes that are accessible only if probed are called probe pins (PP).

Net Dependency Data describes the interrelationship between the input nets (Inets) and dependent nets (Dnets). Inets control the state of Dnets. Come- From-Dependency data lists Inets per Dnet and logic circuitry between Inets and Dnet. Go-To-Dependency data lists Dnets per Inet.

Logic Test consists of logic state (1, 0, X,) tests. PIO and PP expected responses are referenced by test number of PI stimulus that caused them. PIO and PP are monitored after each stimulus. Test with smaller test number represents an earlier point in Logic Test. Tester monitors the Logic Test in logic steady-state mode, glitch mode, or both. Analog voltage measurement is made at the first encountered logic "1" and logic "0" state per PIO and per probed PP. Tester can perform open, short, and resistance test between all physically monitored nodes (PIO and probed PP).

PROBE Algorithm (PROBE): PROBE is tailored to card technology and tester used. PROBE functions are (a) determine what node to probe, (b) determine what tests to apply, and (c) evaluate collected data and determine whether to continue probing or to diagnose defects. Each diagnosed defect must be fixed before another defect on assembly is diagnosed. The flow chart describes PROBE.

Apply Nonlogic Tests (BLK 1): Nonlogic tests include OPEN, SHORTS and RESISTANCE (power-off) tests, Tester setup test, and self-test. These tests are applied to voltage and signal nets. If no Nonlogic failures are detected then PROBE applies Logic Test (BLK 4). Stimuli are applied to first failing test number (FFT). Store FFT and associated failure type per failing PIO. If the card does not fail...