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Antisaturation Clamp for XOR Circuit

IP.com Disclosure Number: IPCOM000084813D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Swietek, D: AUTHOR

Abstract

In a logic masterslice layout for providing T/2/L AND-INVERT circuits, exclusive OR circuits may be readily implemented. As seen from Figs. 1 and 2 of the drawing, the components of a single T/2/L circuit are interconnected to provide an exclusive OR (XOR) circuit.

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Antisaturation Clamp for XOR Circuit

In a logic masterslice layout for providing T/2/L AND-INVERT circuits, exclusive OR circuits may be readily implemented. As seen from Figs. 1 and 2 of the drawing, the components of a single T/2/L circuit are interconnected to provide an exclusive OR (XOR) circuit.

Attention is directed to the connection of Schottky barrier diode D1 in Fig. 2. This connection provides a clamping circuit comprised of diode D1 and resistors R2, R3 and R4 which effectively limits the level at which the collector nodes of transistors T2 and T3 may fall. This clamping circuit minimizing the saturation of transistors T2 and T3.

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