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Pulse Code Modulation Word Adder

IP.com Disclosure Number: IPCOM000084832D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Dauby, A: AUTHOR [+2]

Abstract

The circuit shown allows the Pulse Code Modulation (PCM) companded words A and B to be added in an economical way using transistor-transistor logic (TTL).

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Pulse Code Modulation Word Adder

The circuit shown allows the Pulse Code Modulation (PCM) companded words A and B to be added in an economical way using transistor-transistor logic (TTL).

8-bit companded PCM words are expressed by a sign bit S, three segment bits TUV and four linear bits WXYZ. All the possible values of sign bit S and segment bits are represented in the left part of the following table. The corresponding linear 12-bit words are expressed in the right part.

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8-bit companded words A and B stored in registers 1 and 2 are applied to two read-only memories 3 and 4,wherein they are expanded to linear 12-bit signed 2's complement according to the above table by table look-up procedures.

Linear 12-bit representations of A and B are provided on output busses 5 and 6 and are applied to a 12-bit adder 7. The result of the addition is a signed 2's complement 12-bit word on output 7-1 to 7-12. Output 7-1 gives the most significant sign bit and output 7-12 gives the last significant bit.

Outputs 7-1 to 7-8 are connected by bus 8 to a read-only memory 9, which by table look-up procedures gives the sign bit S and the three-segment bits on its outputs 9-1 to 9-4.

As is shown by the table, depending upon the value of the segment bits, bits w, x, y and z of the linear representation are on determined outputs 7-3 to 7-12. Consequently, in order to compand the linear 12-bit result, a selection is made amongst bits on outputs 7-3 to 7-12...