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Two Bit Words Comparison Circuit

IP.com Disclosure Number: IPCOM000084837D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Gautier, Y: AUTHOR [+2]

Abstract

Proposed is a logic comparison circuit utilizing complementary metal-oxide semiconductor (MOS) technology for comparing two words of two bits each, i.e., A1A2 and A'1A'2, the primes (') indicating the homologous bits.

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Two Bit Words Comparison Circuit

Proposed is a logic comparison circuit utilizing complementary metal-oxide semiconductor (MOS) technology for comparing two words of two bits each, i.e., A1A2 and A'1A'2, the primes (') indicating the homologous bits.

The proposed circuit 10 comprises two main logic blocks. The first of these 11, which consists of N-channel field-effect transistors (FET's) connected between the output terminal 12, and the ground terminal 13, performs the logic function (A1A'1+A1A'1)(A2A'2+A2A'2). The second logic block 14, which is complementary to the first, is connected between the supply +V and the output terminal 12.

On the one hand, block 14 includes four conventional inverters 15, 16, 17, 18 which are connected between the supply +V and the ground terminal and are, respectively, fed with bits A1, A'1, A2, A'2. On the other hand, an intermediate logic block 19 comprises four P-channel FET's, each of which receives both the output from the associated inverter on its drain electrode and the complement value of the corresponding homologous bit on its gate electrode. The second logic block 14 performing the function (A1A'1+A1A'1)+(A2A'2+A2A'2). It should be noted that the complement values of the four binary inputs, i.e., A1,A'1, and A2, A'2, obtained at the respective outputs of the inverters are also fed to the first logic block 11.

The combination of the two complementary blocks 11 and 14 precludes the possibility of a short occurring between...