Browse Prior Art Database

Dynamic Associative FET Memory Cell

IP.com Disclosure Number: IPCOM000084843D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Baitinger, U: AUTHOR [+3]

Abstract

The drawing shows a dynamic memory cell for store, write and compare operation modes. Field-effect transistors (FETs) 1 and 2 together with storage capacitors 3 and 4, form a dynamic memory cell with an associated word or write line WL and bit lines B0, B1. By adding further FETs 5, 6 and compare line CL, the cell is rendered capable of carrying out the above-mentioned associative function. For illustration purposes, the FETs are assumed to be N-channel enhancement field-effect transistors.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 76% of the total text.

Page 1 of 2

Dynamic Associative FET Memory Cell

The drawing shows a dynamic memory cell for store, write and compare operation modes. Field-effect transistors (FETs) 1 and 2 together with storage capacitors 3 and 4, form a dynamic memory cell with an associated word or write line WL and bit lines B0, B1. By adding further FETs 5, 6 and compare line CL, the cell is rendered capable of carrying out the above-mentioned associative function. For illustration purposes, the FETs are assumed to be N-channel enhancement field-effect transistors.

The search information to be compared with the stored information at nodes N1, N2 is applied to bit lines B0, B1, e.g., OV/3V. The potential of compare line CL then indicates the compare result.

Each compare line CL common to a row of cells is connected to an output driver circuit 7 comprising transistor 8 for restoring the compare line to VH, and also comprising transmission gate transistor 9 followed by the bootstrap output stage with transistor 10 and capacitor 11, which is controlled by the DR pulse and delivers the output signal of compare line CL.

A "match" result keeps the CL potential up, because there is no current flow through FET 5, 6. A "mismatch" causes a current flow in one branch through FET 5 and 6, respectively, resulting in the CL potential being drawn down, as illustrated in the drawing. During the compare operation the word/write line potential of WL and the restore potential at R are kept down. Writing and refreshing are...