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Invalidate Page Table Entry Procedures

IP.com Disclosure Number: IPCOM000084868D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Junod, DM: AUTHOR [+2]

Abstract

This procedure allows deletion of page table entrys in Central Processing Units (CPU's) of a multiprocessing (MP) system.

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Invalidate Page Table Entry Procedures

This procedure allows deletion of page table entrys in Central Processing Units (CPU's) of a multiprocessing (MP) system.

On entering the Invalidate Page Table Entry (IPTE) instruction, microcode sends a "Sync Request" to other CPU's of the MP system. The "Sync" received by the remote CPU initiates a microcode quiesce as it would in the case of a store security key instruction (SSK). When the microcode has entered this pseudo wait state, a "Response" is returned to the sending CPU.

While waiting for Response, the CPU executing the IPTE fetches the Page Table Entry to obtain the real address of the Page Origin. The pointer to the Page Table Entry is the address found in the register designated by the B2 field of the IPTE instruction. Two Insert Storage Keys (ISKs), addressing the Page Origin and Page Origin +2K, obtain the keys for both 2K protected segments of a 4K page.

When response is received, acknowledging that the remote CPU is quiesced, the Page Table Entry's Invalidation Bit would be "OR"ed on. SSK microcode would then be executed, using the key obtained by the ISK to keep the key unchanged. The SSK mechanism will cause both CPU's to invalidate their Directory Lookaside Table (DLATs) for that 2K block. If Sync Request is left on, then the receiving CPU will be ready for a second SSK as soon as the first has completed. The second SSK would be executed by microcode to invalidate the second 2K of the 4K page. After both...