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Multiple Instruction Stream Uniprocessor

IP.com Disclosure Number: IPCOM000084872D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Preiss, RJ: AUTHOR

Abstract

A uniprocessor can simultaneously run two instruction streams by having hardware features including two sets of program status word (PSW) registers, two sets of control registers, two sets of general purpose registers, two sets of floating-point registers, two sets of timers, means for partitioning storage between the instruction streams, means for allocating instruction time slices between the instruction streams, and means for steering interrupts to the desired instruction stream.

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Multiple Instruction Stream Uniprocessor

A uniprocessor can simultaneously run two instruction streams by having hardware features including two sets of program status word (PSW) registers, two sets of control registers, two sets of general purpose registers, two sets of floating-point registers, two sets of timers, means for partitioning storage between the instruction streams, means for allocating instruction time slices between the instruction streams, and means for steering interrupts to the desired instruction stream.

Two independent operating systems can run concurrently on the uniprocessor without suffering the overhead usually associated with a programmed hypervisor. Also, direct execution of I/O instructions (rather than interpretive execution via a hypervisor) is permitted so as to make it possible for each operating system to handle its own I/O devices in its own way.

This multiinstruction-stream uniprocessor can be generalized to more than two instruction streams, by duplicating the above-described hardware features by the number of instruction streams to be supported. These features are described in more detail, as follows:

1. Instruction Stream Identification: Each instruction stream is assigned an identifier (ID) which addresses an assigned PSW register and other duplicate registers and timers, which together are considered as the assigned "processor". Switches on the console are provided so that an instruction stream may be identified for manual operations, such as IPL, Start, Stop, etc. The IBM S/370 SIGP instruction permits program communication between the instruction streams. The S/370 Start I/O instruction signals to the addressed subchannel the instruction stream identity to which I/O interrupts must be returned.

2. Storage Partitioning: The storage needed to run each instruction stream is assigned to the instruction strea...