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Analog To Digital Converter for Josephson Tunneling Memory

IP.com Disclosure Number: IPCOM000084900D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Fang, FF: AUTHOR [+2]

Abstract

Fig. 1 shows an analog-to-digital converter which incorporates, for each stage, a multicontrol logic gate. Thus, in Fig. 1, current IG1 flows through gate G1 or, if gate G1 is switched, through resistor R1. Gate G1 is controlled by a control line through which analog data Ia flows and by a bias current r2 which opposes the direction of analog signal flow.

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Analog To Digital Converter for Josephson Tunneling Memory

Fig. 1 shows an analog-to-digital converter which incorporates, for each stage, a multicontrol logic gate. Thus, in Fig. 1, current IG1 flows through gate G1 or, if gate G1 is switched, through resistor R1. Gate G1 is controlled by a control line through which analog data Ia flows and by a bias current r2 which opposes the direction of analog signal flow.

Similarly, current IG2 flows through Josephson device G2 or, if the latter is switched, through a resistor R2. Josephson device G2 is controlled by the analog data, Ia, by a bias current r1 which is oppositely directed to the analog current, Ia, and by current IG1 if gate G1 switches.

In like manner, current IG3 flows through either gate G3 or resistor R3 if the former switches. Gate G3 is controlled by analog data current, Ia, and by oppositely directed bias currents r0, IG2 and IG1 if they are present as a result of the switching of gates G2 and G1, respectively.

In Fig. 1 the resistances are related to the bias currents as follows:

R1 : R2 : R3 = 1 over r2 : 1 over r1 : 1 over r0.

The gates G1 to G3 are designed as follows:

Gate 1 O/P If Ia > r2 02 = r2

Ia < r2 02 = 0

Gate 2 O/P If (Ia - 02) > r1 01 = r1

(Ia - 02) < r1 01 = 0

Gate 3

If (Ia - 02 - 01) > r0 00 = r0

(Ia - 02 - 01) < r0 00 = 0 where r2, r1 and r0 are reference currents corresponding to an analog current of 2/2/, 2/1/ and 2/0/, respectively.

In operation, an analog data signal, Ia, is applied to the analog data control line. At the same time, bias r2, in opposition to the analog data signal, is applied to gate G1. If the analog signal does not exceed the...