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A D and D A Conversion System for A Law Pulse Code Modulation

IP.com Disclosure Number: IPCOM000084910D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Peled, A: AUTHOR

Abstract

The CCITT type A-law defines a companded quantization law, which assigns fine quantization steps to small input signals and coarser quantization levels to larger signals, thus maintaining a constant signal-to-noise ratio over a large dynamic range. Fig. 1 illustrates the mapping performed by this code. The code is extended symmetrically for negative values of the input. The seven bits that represent the absolute quantized value of the input are determined as follows: 1. The first three bits are determined according to the segment in which the input lies, e.g., if the input has a value between v(3) > x > v(4), then it lies in segment 5 and its code is 101. 2. The last four bits are determined by dividing each segment into 16 fine partitions and determining in which fine partition the input lies, e.g.

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A D and D A Conversion System for A Law Pulse Code Modulation

The CCITT type A-law defines a companded quantization law, which assigns fine quantization steps to small input signals and coarser quantization levels to larger signals, thus maintaining a constant signal-to-noise ratio over a large dynamic range. Fig. 1 illustrates the mapping performed by this code. The code is extended symmetrically for negative values of the input. The seven bits that represent the absolute quantized value of the input are determined as follows: 1. The first three bits are determined according to the segment in which the input lies, e.g., if the input has a value between v(3) > x > v(4), then it lies in segment 5 and its code is 101. 2. The last four bits are determined by dividing each segment into 16 fine partitions and determining in which fine partition the input lies, e.g., for the previous example of:

(Image Omitted)

then it lies in the eighths partition and its code is 1000.

Fig. 2 comprises a block diagram of the conversion method for an analog/digital (A/D) and a digital/analog (D/A) conversion system.

The reference waveform generator (RWG) generates a periodic waveform as depicted in Fig. 3. The voltage V(REF) (t) is held constant for T(H) seconds (S1, S2, S3 switches in Fig. 2 are open) and is allowed to decay exponentially for T(D) seconds (S2 closed) such that:

(Image Omitted)

This is repeated 8 times and the ninth time S3 is closed to make the output voltage V(REF)(t) = 0 for T(H) seconds. During the time T(1) to T(c) the capacitor CO is recharged to V(REF) (switch S1 closed). The reason for holding V(REF) (t) constant for T(H) seconds on each voltage level V(1) to V(9), is to allow the use of simple and inexpensive sample and hold circuits in the individual comparator and linear interpolators and linear output interpolators (CLI/LOI's). This reference waveform V(REF)(t) is distributed to the individual CLI's and LOI's.

The CLI has two sample and hold modules that sample the reference waveform V(REF)(t) alternately, thus at point A in Fig. 2 the levels V(1), V(3), V(5), V(7), V(9) appear sequentially and at point B the levels V(2), V(4), V(6), V(8) appear sequentially. The input signal X(in) is rectified and it's sign is stored in the sign bit of the code register. The rectified value of x, x+ is fed to the comparators, whose output is zero as long as x+ is smaller than their second input.

The fi...