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Controllable Process for Fabricating Short Channel FET Device

IP.com Disclosure Number: IPCOM000084940D
Original Publication Date: 1976-Jan-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Dennard, RH: AUTHOR [+3]

Abstract

A controllable process for fabricating short-channel field-effect transistor (FET) devices is described. The process reduces the bias between a mask (nominal) gate length and the actual (electrical) gate length. The process also minimizes overlap from the gate electrode to the source and drain regions.

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Controllable Process for Fabricating Short Channel FET Device

A controllable process for fabricating short-channel field-effect transistor (FET) devices is described. The process reduces the bias between a mask (nominal) gate length and the actual (electrical) gate length. The process also minimizes overlap from the gate electrode to the source and drain regions.

Shown in Fig. 1 is an intermediate step in a process that can be used for fabricating self-aligned silicon gate FET devices by ion implantation. A silicon- nitride mask is used to delineate the etching of a polysilicon gate. To ensure complete removal of the silicon-nitride mask outside the gate area the Si(3)N(4) must be slightly overetched. This makes the length of the silicon-nitride mask less than the original (optical) mask length L(MASK), as shown in Fig. 1. The length of the polysilicon gate is further reduced by chemical etching.

Subsequently the Si(3)N(4) is removed and the polysilicon is used as an ion- implantation mask to delineate the channel region, as shown in Fig. 2. Since the chemical etch used to delineate the poly-Si leave approx. 45 degrees slope on the edges of the poly-Si, the edge of the implantation likewise has approx. a 45 degrees slope, as shown in Fig. 2. This causes a further reduction in the electrical channel length below the mask dimension, since the implanted ions penetrate the edges of the mask forming doped n+ regions extending under the edges of the silicon gate. A typical value for quantity Delta L = (L(MASK) - L(ELECTRICAL)) for progresses similar to that just descrided in Fig. 1, is 1 Micron. This quantity decreases allowable...