Browse Prior Art Database

Driver Circuit Having Controllable Inactive Time

IP.com Disclosure Number: IPCOM000084943D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Bigbie, SE: AUTHOR [+3]

Abstract

In applications such as wire driving for matrix printers, a load device can be damaged by operation at an excessive repetition rate. Many such loads also are located in electrically noisy environments, or produce noise themselves.

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Driver Circuit Having Controllable Inactive Time

In applications such as wire driving for matrix printers, a load device can be damaged by operation at an excessive repetition rate. Many such loads also are located in electrically noisy environments, or produce noise themselves.

Driver circuit 100, Fig. 1, avoids these and other problems by providing an inactive or refractory time period after each output pulse, during which no further pulse can be produced. For a quiescent uplevel at input 101, inverter 110 has a down output, and timer 120 is timed out with an uplevel output 121. The output 131 of Schmitt trigger 130 is down, as are the inputs and the outputs of inverters 140 and 150, and the driver circuit output 102 from predriver 160. Bias circuit 170 supplies potentials I and VR for one or more triggers 130.

Upon a negative transition in the wavefonm 201 (Fig. 2) at input 101, inverter 110 discharges the capacitor of timer 120, to hold output 121 low as long as input 101 remains down. The output of inverter 150 also goes down, disabling inverter 140 and grounding output 131 of trigger 130. Output 102 goes up to energize the load, not shown, while input 101 remains down, as shown in output waveform 202, Fig. 2. When input 101 returns to an uplevel, inverter 150 becomes nonconducting, allowing trigger output 131, shown in waveform 231, Fig. 2, to clamp the output of inverter 110 to a downlevel through inverter 140. Timer output 121 then ramps upwardly, as show...