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High Speed Combinatorial Logic Bit Shifter

IP.com Disclosure Number: IPCOM000084944D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Doty, KL: AUTHOR [+2]

Abstract

Fig. 1 shows a basic shift cell (BSC) for gating one of three data inputs Xn-i, Xn and Xn+i to an output line Yn. When a shift-enable line SEi is 0, inverter N gates input Xn through the center AND to Yn. When SEi is 1, data bit Xn-i is gated to Yn when right-shift line RS is 1. When left-shift line LS is 1, bit Xn+i is passed to Yn.

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High Speed Combinatorial Logic Bit Shifter

Fig. 1 shows a basic shift cell (BSC) for gating one of three data inputs Xn-i, Xn and Xn+i to an output line Yn. When a shift-enable line SEi is 0, inverter N gates input Xn through the center AND to Yn. When SEi is 1, data bit Xn-i is gated to Yn when right-shift line RS is 1. When left-shift line LS is 1, bit Xn+i is passed to Yn.

Fig. 2 shows an array of BSC stages for shifting four-bit words right or left from zero to three positions. A desired shift count is held in a register, not shown, having output bits SE1 and SE2. Since the X0-X3 data inputs are each coupled to two immediately adjacent BSC's in the upper row, the state of the SE1 bit shifts the data by either zero or one position right or left. In a similar manner, the state of SE2 controls the second row to shift data either zero or two positions right or left. Thus, any total shift amount from zero to 3 can be specified by the two SE lines.

When the RS line in Fig. 2 is a 1, a shift specified by the SE lines takes place to the right. A 0 on the CRS line causes a "logical" shift; i.e., 0's are entered on the left. A 1 on the CRS line causes a "circular" shift, wherein the data shifted off the right end are reentered to the left. The LS and CLS lines operate similarly for left logical and circular shifts.

The array of Fig. 2 may be extended to accommodate any number of data bits. One BSC is added to each row for every data bit, and one row is added for every two-fold (or fraction thereof) increase in the maximum number of shift positions. The data outputs from each previous row are spaced 2/i/ stages apart in the next row, wher...