Browse Prior Art Database

Digital Pulse Filter and Delay

IP.com Disclosure Number: IPCOM000084945D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Walewski, LG: AUTHOR

Abstract

Circuit 10 eliminates short pulses of either polarity from a digital input signal. When input signal 11 is an "uplevel" the output of inverter 12 is a short to ground, while a "down" input causes the inverter output to be an open circuit. For a negative transition in signal 11, capacitor 13 charges from a positive voltage V+ through resistor 14 until the capacitor voltage is sufficient to switch inverter 15. If a positive transition occurs before this point, no negative transition will take place at the output of inverter 15. If no such positive transition occurs, the negative transition is delayed by a predetermined interval from that at the input 11.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 90% of the total text.

Page 1 of 2

Digital Pulse Filter and Delay

Circuit 10 eliminates short pulses of either polarity from a digital input signal. When input signal 11 is an "uplevel" the output of inverter 12 is a short to ground, while a "down" input causes the inverter output to be an open circuit. For a negative transition in signal 11, capacitor 13 charges from a positive voltage V+ through resistor 14 until the capacitor voltage is sufficient to switch inverter 15. If a positive transition occurs before this point, no negative transition will take place at the output of inverter 15. If no such positive transition occurs, the negative transition is delayed by a predetermined interval from that at the input 11.

Components 16-19 operate in the same manner. Inverter 16, however, is coupled to input signal 11 through another inverter 20, so that the output of inverter 19 filters and delays positive transitions instead of negative ones. The outputs of inverters 19 and 15 drive the set and reset terminals of flip-flop 21, so that single-rail output signal 22 follows input 11, except that short pulses of either polarity are eliminated, and transitions are delayed. The delay period is independent of the repetition rate and duty cycle of input 11, since capacitors 13 and 17 are discharged quickly before a new delay period is started.

If resistors 14 and 18 are unequal, different delay periods may be obtained for positive and negative pulses. If they are equal, circuit 10 operates as an ideal low-pas...