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Ram Latch Configuration

IP.com Disclosure Number: IPCOM000084951D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

A high-speed, low-power latch and gate are formed by integrated circuit techniques from basic NOR and OAI circuits. These NOR and OAI circuits can be size, power, or performance specified.

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Ram Latch Configuration

A high-speed, low-power latch and gate are formed by integrated circuit techniques from basic NOR and OAI circuits. These NOR and OAI circuits can be size, power, or performance specified.

Latch 10 is schematically illustrated in Fig. 1 as including OAI block 15, invert 20 and OAI block 25. The output of block 15 feeds blocks 20 and 25; whereas, the output of invert 20 feeds back to OAI 15. The output of latch 10 is taken from OAI 25 which functions as a NAND. Data IN, -Set and +Reset lines 16, 17 and 18, respectively, are applied to OA1 15. Latch 10 is addressed by lines connected to NOR circuit 30 which functions as a decoder. The output of NOR 30 is connected as a Read input into OAI 25, whereby together with the input from OAI 15 the NAND function is obtained.

The particular configuration of latch 10, Fig. 1, facilitates the physical arrangement shown in Fig. 2. Circuit 20 is outboard to the right to enable diffusion connections from circuits 15 and 20 to load devices 19 and 21, respectively. There is no load device connected to circuit 25; hence it is positioned outboard to the left.

Metal land connection 22 forms the feedback from circuit 20 to circuit 15. Output diffusion 23 provides the forward connection between circuits 15 and 20.

Metal land 26 connects circuit 15 to circuit 25. Read input from NOR 30 is over metallized line 31. Data Out is metallized line 28 connected to circuit 25 via output diffusion 27. This arrangement is on...