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Bit Addressable Storage Access System

IP.com Disclosure Number: IPCOM000084952D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 5 page(s) / 112K

Publishing Venue

IBM

Related People

Doty, KL: AUTHOR [+2]

Abstract

A circuit arrangement is provided to facilitate bit level addressing of binary data bit strings of arbitrary length. The arbitrary length data bit strings are fetched as fixed-length bytes or words from conventional storage and presented to the processor operation register as a continuous sequence of register loadings, where the least significant bit of the string occupies the least significant bit position of the operation register, and all bits of the register to the left of the most significant bit of the bit string on the final loading are set to zero or sign extended.

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Bit Addressable Storage Access System

A circuit arrangement is provided to facilitate bit level addressing of binary data bit strings of arbitrary length. The arbitrary length data bit strings are fetched as fixed-length bytes or words from conventional storage and presented to the processor operation register as a continuous sequence of register loadings, where the least significant bit of the string occupies the least significant bit position of the operation register, and all bits of the register to the left of the most significant bit of the bit string on the final loading are set to zero or sign extended.

A string of bits of arbitrary length are presented by the processor for storage as a sequence of fixed-length bytes or words. The least significant bit of the string is the least significant bit of the first word or byte stored, and is shifted left an amount necessary to cause the resulting position thereof to correspond to a specified initial bit address. All successive bits of the first and successive words or bytes are shifted by a like amount to form a sequence of words or bytes stored in word or byte addressable sequential locations, but in such a way that bits not within the bit address boundaries remain unaltered.

When fetching a specified bit string from storage, not shown, initial and final bit addresses (each including a byte address and an additional 3 bits to specify bit position within the addressed byte) are loaded into registers 10 and 20, respectively. At the same time the initial byte address is loaded into current address register 15. Register 15 is incremented in the usual manner. The first byte of data fetched from storage is entered into register 23 via gate 21 and bit suppression logic 22. Gate 21 is controlled by a FETCH CTRL 1 signal. This first byte of data contains at least the initial bits of the bit string and is transferred to register 27 via gate 25 and OR circuit 26, as the second byte of data is transferred from storage into register 23. Gate 25 is controlled by a FETCH CTRL 2 signal. If the bit string ends within the first byte fetched, register 23 would be reset.

The contents of registers 23 and 27 are shifted through bit shifter network 30, which is shown in greater detail in Fig. 2. The number of positions shifted is governed by the value of the initial bit address in register 10. Bit shifter 30, Fig. 2, includes combinatorial logic shift cells L, R and RL which are connected for left shift, right shift and right and left shifts, respectively. Logic for the RL cell is shown in Fig. 3. The R and L cells are similar but require one less AND gate. The line RS CTRL is active for a right shift and inactive for a left shift. Inverter 31 functions to convert the inactive RS CTRL signal into an active signal for left shift.

Shifter 30 has fifteen bit inputs labeled X0-X14 in Fig. 2. Shift enable control signals SEl, SE2 and SE3 are from register 10 and are determined by the contents thereof. These...