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Two Phase Capstan Tachometer Check

IP.com Disclosure Number: IPCOM000084964D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Pisciotta, EC: AUTHOR

Abstract

The circuitry, as depicted schematically, shows check means which ensure that the output from a two-phase tachometer is in proper sequence. During this test, phase A and phase B of the tachometer are monitored by the circuit shown in Fig. 1.

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Two Phase Capstan Tachometer Check

The circuitry, as depicted schematically, shows check means which ensure that the output from a two-phase tachometer is in proper sequence. During this test, phase A and phase B of the tachometer are monitored by the circuit shown in Fig. 1.

In operation, any transition occurring on phase A (Ph. A) will cause a pulse on output 1. The width of the pulse on output 1 is equivalent to the time between the rise of clock 10 and the rise of clock 12. Likewise, any transition occurring on phase B (Ph. B) will cause a pulse at output 2, the width of the pulse at output 2 being the same as the width of the pulse at output 1. The signal on output 1 and the signal on output 2 are then fed to the countup/countdown input of an up-down counter (1 output to the countup input, 2 outputs to the countdown input).

As the motor to which the two-phase tachometer is attached turns creating tachometer transitions, the counter will be alternately incremented or decremented. If either tachometer should fail (but not at the same time), the counter, not shown, will only be incremented or decremented depending on which tachometer failed. By selecting a predetermined range, whenever the count falls outside of the range, it is an indication of malfunction.

Fig. 2 depicts a tachometer absent test. For this test, one phase of the tachometer (example, Ph. B) is monitored during a predetermined checking interval. In Fig. 2, the checking intervals are 1 msec and 1...