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An Ultra-Thin High Dielectric-Constant Interface for High Performance CMOS Devices Using a Controlled-Dosage Implantation Doping Technique

IP.com Disclosure Number: IPCOM000084989D
Publication Date: 2005-Mar-02
Document File: 4 page(s) / 297K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that creates an ultra-thin high-k (dielectric constant) interface by using low energy ion implantation, or the plasma doping of metallic impurities such as Ti, Hf, Zr. This process is followed by oxidation to form the metal oxide or metal silicate layer in direct contact with pure silicon. Benefits include avoiding the formation of a low dielectric constant SiOx interfacial layer.

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An Ultra-Thin High Dielectric-Constant Interface for High Performance CMOS Devices Using a Controlled-Dosage Implantation Doping Technique

Disclosed is a method that creates an ultra-thin high-k (dielectric constant) interface by using low energy ion implantation, or the plasma doping of metallic impurities such as Ti, Hf, Zr. This process is followed by oxidation to form the metal oxide or metal silicate layer in direct contact with pure silicon. Benefits include avoiding the formation of a low dielectric constant SiOx
interfacial layer.

Background

A high performance CMOS logic device requires a 0.5 nm EOT gate dielectrics for 32 nm node technologies. The high- dielectric constant gate dielectrics currently formed by MOCVD, ALD or CVD methods do not promote ideal growth on H-terminated silicon. A relatively thick SiO2 oxide interface is commonly used (normally 1 nm), forming a low capacitance layer in series with the high-k material, but it dominates the overall capacitance and prevents scalability to EOT<0.5 nm (see Fig. 1). In addition, interfacial reactions from high-k dielectrics with silicon lead to degradation of the dielectric properties. For example,  the high-k dielectric reacts with H-terminated silicon at an elevated temperature to form a low-k silicate layer

General Description

In the disclosed method, ion implantation or the plasma doping of metallic impurities is performed on the silicon wafer with intentionally grown SiO2, and/or Si3N4 layers. The film thickness is very important for controlling the position of the impurity peak concentration. The wafer cleaning prior to oxidation is a standard cleaning process. The disclosed method is applicable to any type and any size of silicon wafer.

In one implementation of the disclosed method, the ion implantation of metallic ions (Hf+, Zr+, or Ti+)  is done through the SiO2 by placing the peak con...