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In Situ Polycrystalline Silicon Deposition Process for Silicon Gate FET Devices

IP.com Disclosure Number: IPCOM000085024D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Doulin, J: AUTHOR [+3]

Abstract

Dielectric breakdown of the gate insulator in insulated gate field-effect transistors (IGFET's) is a known reliability concern. Substantial differences in failure rates have been attributed to the nature of the gate electrode. Polycrystalline silicon is a reliable electrode material.

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In Situ Polycrystalline Silicon Deposition Process for Silicon Gate FET Devices

Dielectric breakdown of the gate insulator in insulated gate field-effect transistors (IGFET's) is a known reliability concern. Substantial differences in failure rates have been attributed to the nature of the gate electrode. Polycrystalline silicon is a reliable electrode material.

An advantageous "in situ" 800 degrees C deposition process for the fabrication of polycrystalline silicon electrodes is set forth below.

The process consists of an argon and hydrogen purge at 800 degrees C followed by silicon deposition for three minutes. Subsequent simultaneous depositions of silicon and phosphine PH(3) doping is then allowed to occur for two additional minutes. The key to this process is the optimum time lag of three minutes prior to the introduction of dopant. Without this time lag, inversion of a P- type silicon surface will occur. Low-charge levels of 3 x 10/10/ charges/cm/2/ have been obtained on capacitors with oxides of 700 Angstroms. It is to be appreciated that a dopant other than phosphorous, for example, boron or arsenic may be employed.

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