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Configuring Shift Register Latch Chains for Delay Measurements

IP.com Disclosure Number: IPCOM000085035D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Hack, GE: AUTHOR

Abstract

Many computers are designed such that all system latches are connected, or connectable, into a series of SRL's (shift register latches). This permits all internal latches to either be set to a known state or to be read out. This configuration aids in testing and diagnosis.

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Configuring Shift Register Latch Chains for Delay Measurements

Many computers are designed such that all system latches are connected, or connectable, into a series of SRL's (shift register latches). This permits all internal latches to either be set to a known state or to be read out. This configuration aids in testing and diagnosis.

With the addition of some circuitry and by setting the clocks to the SRL's in the proper quiescent state, each of the SRL's can be selectively made to oscillate as a recirculating loop. In this manner, average delay information can be derived without sophisticated software or hardware additions to circuit testers.

Reference is made to the drawing. Two controls are shown for the additional circuitry. +TEST connects the input of an addressed SRL to its output, thereby making it a recirculating loop. When +TEST is not activated, the SRL's function in their normal manner. The ODD/EVEN control allows this circuitry to function for SRL chains that have either an even or an odd number of logical inversions, an odd number of inversions being required to make the chain oscillate.

With the addition of a very minimal amount of circuitry to a computer or system, a DC type logic tester, not shown, in conjunction with a frequency counter, not shown, can make average delay measurements to the SRL portion of the system.

It is to be appreciated that all or a portion of the circuitry depicted in the drawing may be contained on a semiconductor chip fa...