Browse Prior Art Database

Inhibit Circuit and Layout

IP.com Disclosure Number: IPCOM000085038D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+2]

Abstract

The inhibit input of the circuit depicted in Fig. 1 may be utilized prior to an emitter-follower off-chip driver or send circuit on a T/2/L logic masterslice chip, to force the driver into its high-impedance state. The "inhibit" feature has particular utility in the testing of higher level assemblies of integrated circuits.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Inhibit Circuit and Layout

The inhibit input of the circuit depicted in Fig. 1 may be utilized prior to an emitter-follower off-chip driver or send circuit on a T/2/L logic masterslice chip, to force the driver into its high-impedance state. The "inhibit" feature has particular utility in the testing of higher level assemblies of integrated circuits.

The circuit of Fig. 1 may be implemented in a random-logic masterslice chip layout as depicted in Fig. 2.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]