Browse Prior Art Database

Implanted Resistor Formed After the Formation of the Emitter in a Transistor Process

IP.com Disclosure Number: IPCOM000085039D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 109K

Publishing Venue

IBM

Related People

Barile, CA: AUTHOR [+4]

Abstract

This process provides an implanted resistor having tight tolerances, low temperature coefficient of resistance and low voltage coefficient of resistance utilizing a minimum of process steps.

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Implanted Resistor Formed After the Formation of the Emitter in a Transistor Process

This process provides an implanted resistor having tight tolerances, low temperature coefficient of resistance and low voltage coefficient of resistance utilizing a minimum of process steps.

Fig. 1 illustrates a semiconductor substrate 2 containing an N/+/ subcollector region 8 and a P-type base region surrounded by dielectric isolation regions, denoted ROI. The surface of the substrate is covered by silicon dioxide, which is the result of the standard processing steps and includes the base reoxidation.

In Fig. 2, a layer of silicon nitride is formed atop the thermal SiO(2) layer. Another SiO(2) layer, typically pyrolytically deposited, is deposited atop the silicon nitride layer for masking purposes. The thickness of the nitride layer is selected so as to optimize the resistor tolerance with respect to the resulting dielectric thickness for a particular ion implant energy.

As illustrated in Fig. 3, an N/+/ emitter region 4 is then formed in the P base region through the composite dielectric coating. After the emitter region is formed, resistors are implanted into the N-type epitaxial region 5. The implantation is done through the composite silicon nitride/silicon dioxide layer disposed above the epitaxial layer. The pyrolytically deposited layer is removed prior to the implantation.

The implanted devices are then annealed in a standard manner and base contacts are opened. Proces...