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Single Cell Exclusive OR Circuit

IP.com Disclosure Number: IPCOM000085040D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+2]

Abstract

The circuit depicted in Fig. 1 performs the exclusive OR (XOR) logical function. The circuit is compatible with T/2/L technology.

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Single Cell Exclusive OR Circuit

The circuit depicted in Fig. 1 performs the exclusive OR (XOR) logical function. The circuit is compatible with T/2/L technology.

The solid line version of the circuit of Fig. 1 may be implemented on a logic masterslice chip layout, as shown in Fig. 2.

An undesirable clamping action is experienced under certain conditions by the logic stage, not shown driving the circuit of Fig. 1 (solid lines). An alternative implementation, obviating the undesirable clamping action, is depicted in Fig. 1 where dotted line connections replace the solid line connections to the input transistor bases. The dotted line connection also provides the interbase resistors R1 and R2.

The broken line implementation of the circuit of Fig. 1 which includes interbase resistors R1 and R2, raises the clamped uplevel of the input of the XOR circuit of Fig. 1 by several hundred millivolts, thus improving its uplevel noise tolerance.

The broken line version of the circuit of Fig. 1, including interbase resistors R1 and R2, may be implemented on a logic masterslice chip layout as shown in Fig. 3.

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