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Digital Filter Architecture

IP.com Disclosure Number: IPCOM000085047D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR

Abstract

This is a design for a digital filter using programmable logic arrays (PLA's) which make it possible to rapidly personalize the required filter.

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Digital Filter Architecture

This is a design for a digital filter using programmable logic arrays (PLA's) which make it possible to rapidly personalize the required filter.

Assuming that a three-tap filter is to be designed, the coefficients of which are Alpha, Beta, Gamma, the i/th/ output sample Y(i) will be related to input samples X(i), X(i-1), X(i-2) through the following equation: Y(i) = Alpha.X(i) + Beta.X(i-1) + Gamma.X(i-2).

The input samples are, respectively, fed to shift registers SR1, SR2 and SR3 (see Fig. 1), in series by bit. Each bit cell of the registers is provided with an output tap connected to a coefficient selector. At each bit time, each one of the selectors feeds a full adder Sigma(1), Sigma(2) and Sigma(3) with the bits of Alpha.X(i), Beta.X(i-1) and Gamma.X(i-2) bearing the same weight, respectively. The outputs of the adders, added together into Sigma(4), provide Y(i) in series by bit on output Sigma'(4).

The coefficient selector is represented in Fig. 2. To understand how it works, it should first be noted that the coefficients used here are entire numbers. Thus, any multiplication such as Alpha.X(i) may be obtained by properly shifting X(i) bits, and eventually adding together two or more of the shifted X(i) bits.

While the X bits are serially fed into the shift registers, they should be picked up at each bit time at a proper bit position. The X bit positions named, respectively, x(n), x(n-1), ... x(n-7) are connected to the lines of a decoding matrix. In fact, each of these lines is made of a couple of lines providing true and complement values of X bits, respectively.

Fig. 2 shows a selector capable of providing the coefficients 3, -5, -8, 7, 10, 18, -44, 9, 16, -2. For instance, Alpha = 3 is obtained by applying the contents of bit positions x(n) and x(n-1) to inputs Sigma(11) and...