Browse Prior Art Database

Two Bit Partitioning Driver

IP.com Disclosure Number: IPCOM000085074D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+3]

Abstract

A driver is described which enables two-bit partitioning which has special use in programmed logic arrays.

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Two Bit Partitioning Driver

A driver is described which enables two-bit partitioning which has special use in programmed logic arrays.

The figure shows a push-pull driver which performs the logical OR function. It is comprised of depletion mode transistors 1, 3 and 6 and enhancement mode transistors 2, 4 and 5. The drain of transistor 1 is connected to the drain supply voltage V and has its gate and source electrodes connected to a first node 1. Transistor 2 has its drain connected to the first node 1, its source connected to ground potential, and its gate connected to the logical input A.

Transistor 3 has its drain connected to the drain potential V(D), its source connected to the output node f, and its gate connected to the gate of transistor 2. Transistor 4 has its drain connected to the output node f, its source connected to the ground potential, and its gate connected to the first node 1. Transistors 1, 2, 3 and 4 operate as a simple push-pull driver for the logical input A.

Transistor 5 has its drain connected to the first node, its source connected to the ground potential, and its gate connected to a second logical input B. Transistor 6 has its drain connected to the drain potential, its source connected to the output node f, and its gate connected to the gate of transistor 5. Transistors 1, 5, 6 and 4 operate as a second push-pull amplifier responsive to the logical input B. In overall operation, the circuit output node is off when both A and B are off, a...