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An Enhanced Push Pull NOR

IP.com Disclosure Number: IPCOM000085075D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Chang, HC: AUTHOR

Abstract

A push-pull circuit is described which accomplished the NOR logical function with a relatively high speed.

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An Enhanced Push Pull NOR

A push-pull circuit is described which accomplished the NOR logical function with a relatively high speed.

The figure shows the circuit with the transistors L and L' being depletion mode field-effect transistors (FET) devices and the transistors A, B, C, A', B', C', and X being enhancement mode FET devices. Depletion mode transistors L and L' operate as loads. Transistor L has its drain connected to the drain potential V(DD), and its gate and source connected to a first node N.

Enhancement mode FET transistor A has its drain connected to ground potential, and its gate connected to the logical input A. Transistor L' has its drain connected to the drain potential V(DD), its source connected to the output node V(O), and its gate connected to the first node N. The enhancement mode FET transistor A' has its drain connected to the output node, its source connected to ground potential, and its gate connected to the gate of transistor A.

Transistors L, A, L' and A' operate as a conventional push-pull inverter driver. For example, with the devices being N-channel FETs, a positive pulse at the input terminal A, will turn transistor A on and place a negative going pulse on the node N. This, in turn, places the depletion mode load device L' in a slightly-on state and, with the enhancement mode device A' being on, places a negative going output signal at the output node V(O). When a negative going signal is applied to the gate of devices A and A', no...