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Testable Decode Checking Circuit

IP.com Disclosure Number: IPCOM000085119D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Norton, JS: AUTHOR [+2]

Abstract

If built in large-scale integration (LSI), the one and only one checking circuit for a 1 out of 8 decoder described in the article by D. J. Zimmerman, IBM Technical Disclosure Bulletin, Vol. 17, No. 8, p. 2432, January 1975, is untestable because of limited I/O pins and the inability to use scope probes on the chip. However, if a means of activating pairs of decode outputs is provided, the checker can be made testable by selecting those pairs which produce a single path through the checking circuit, as indicated by the following table.

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Testable Decode Checking Circuit

If built in large-scale integration (LSI), the one and only one checking circuit for a 1 out of 8 decoder described in the article by D. J. Zimmerman, IBM Technical Disclosure Bulletin, Vol. 17, No. 8, p. 2432, January 1975, is untestable because of limited I/O pins and the inability to use scope probes on the chip. However, if a means of activating pairs of decode outputs is provided, the checker can be made testable by selecting those pairs which produce a single path through the checking circuit, as indicated by the following table. Pairs of Pairs of

Decode Decode

Outputs Single Multiple Outputs Single Multiple

Active Path Path Active Path Path

1,2 X 3,5 X

1,3 X 3,6 X

1,4 X 3,7 X

1,5 X 3,8 X

1,6 X 4,5 X

1,7 X 4,6 X

1,8 X 4,7 X

2,3 X 4,8 X

2,4 X 5,6 X

2,5 X 5,7 X

2,6 X 5,8 X

2,7 X 6,7 X

2,8 X 6,8 X

3,4 X 7,8 X .

Fig. 1 shows a decoder configuration in which a minimized number of test lines A-D can be used to force multiple decoder outputs. Appropriate combinations of decoder inputs and activated test lines, in accordance with the above table, enable the testing of every path through the checking circuit. For normal operation of the decoder, test inputs A-D are set to the "0" state.

The inclusion of a parity input P to the decoder configuration also makes it possible to drive all decode outputs inactive, simply by selecting incorrect parity for any given decode input. Thus a "no select" condition may be forced, to test the 8-way inverted input AND circuit portion of the checking circuit. As an alternative to the addition of parity inputs, the no select condition could be forced by employing a further test line to inhibit one of the normal decode outputs.

An alternate way of producing multiple selects is by modifying the conventional input complementing circuits within the decoder, as sh...