Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Magnitude Differencing Circuit

IP.com Disclosure Number: IPCOM000085132D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Critchlow, DL: AUTHOR [+4]

Abstract

Described is a simple circuit which permits the differencing of the magnitudes of two signals, for any combination of signal polarity. In analog circuits, it can be desirable to subtract the magnitudes of two signals to obtain the difference of the amplitudes - for example, this is important in A-to-D conversion. This description presents a simple dynamic circuit which accomplished this result for any combination of polarities of the input signals. The specific implementation is in metal-oxide semiconductor field-effect transistors (MOSFET) circuitry, but extension to other technologies and additional inputs is obvious.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Magnitude Differencing Circuit

Described is a simple circuit which permits the differencing of the magnitudes of two signals, for any combination of signal polarity. In analog circuits, it can be desirable to subtract the magnitudes of two signals to obtain the difference of the amplitudes - for example, this is important in A-to-D conversion. This description presents a simple dynamic circuit which accomplished this result for any combination of polarities of the input signals. The specific implementation is in metal-oxide semiconductor field-effect transistors (MOSFET) circuitry, but extension to other technologies and additional inputs is obvious.

The circuit is shown in the drawing. The output node will algebraically sum the charge delivered to it as a result of transients coupled through the two capacitors CA and CB. The polarity of these transients depends upon the sequence in which the switches are opened and closed. For example, suppose both VA and VD are positive. Initially, switches S1a and S2b are closed, and the output node initialized. Then the switches are opened, and S2a and S1b are closed. Capacitor CA couples in a positive transient from VA, and CB couples in a negative transient from VB. The change in voltage at the output node (if CA=CB) is: Delta Vout = 1/2 (VA-VB) assuming the stray capacitance at the output node is zero. The general expression is: Delta V out = +/- CAVA over CA+CB+CStray +/- CB VB over CA+CB+ CStray assuming the capacitors a...