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Redundancy in Bubble Domain Memories

IP.com Disclosure Number: IPCOM000085136D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 50K

Publishing Venue

IBM

Related People

Cohen, MS: AUTHOR

Abstract

A freeze-bypass shift register in which the order of bubble domains can be changed is used in combination with a major/minor loop memory to provide redundancy. Additional minor loops are provided in each bubble domain chip above the number needed for device operation, assuming complete freedom from defects.

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Redundancy in Bubble Domain Memories

A freeze-bypass shift register in which the order of bubble domains can be changed is used in combination with a major/minor loop memory to provide redundancy. Additional minor loops are provided in each bubble domain chip above the number needed for device operation, assuming complete freedom from defects.

When data are to be written into the chip, gaps are inserted in the data stream (in the major loop) corresponding to those minor loop positions which are defective. Upon readout into the major loop, the gaps are automatically closed. A separate loop (defect register) is provided into which information is written prior to the use of the memory, to define loop positions which are defective. In this way, the defective loops as well as the loop-bypassing scheme are completely transparent to the rest of the memory.

Fig. 1 is a schematic arrangement of a freeze-bypass register while Fig. 2 shows the bubble domain chip layout with redundancy incorporated. The freeze- bypass register of Fig. 1 includes several bit positions A, B, ..., H, together with an empty bit position (EBP). Bubble domains move to the right and follow normal path 10 unless the data order is to be changed. In normal path 10 there is a freeze and I/O position indicated as F.

When it is desired to switch the order of a bit, for instance bits A and B, bit A is brought to the freeze position F in path 10. It is held there while bit B is transferred along path 12 to a position head of bit A. Generally, a bypass control loop is used to send bit B along the path 12. After this, bit A is released and continues its normal movement around the register.

Provision of an I/O position along path 10 means that a gap can be created between any of the bubble domain bits. This procedure is used prior to the operation of transferring freshly written data from the major loop into the minor loops.

Upon transfer of information out of the minor loops to the major loop, gaps have to be closed corresponding to defective minor loops from which information is not taken. For this purpose a freeze-bypass circuit is used, such as that shown in Fig. 1. A bubble (or the absence of a bubble) corresponding to a defective loop is frozen in the freeze position F and all subsequent bubbles are bypassed directly via bypass path 12, thereby closing the defect-related "gap". The number of correctable minor loops is equal to the number of freeze-bypass stations which have been provided.

The major and minor loops in the layout of Fig. 2 are of standard form, except that there are two extra minor loops provided to take the place of possible defective loops, while two freeze-bypass stations are provided both before and after that section of the major loop used for transfer into minor loops. Furthermore, a special register is provided to identify those minor loops which are defective. The output of this register can be fed directly into the same detector as used for readou...