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Submicron FET Process Step Sequence to Provide Multilayer Metal Structure

IP.com Disclosure Number: IPCOM000085146D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Logan, JS: AUTHOR [+3]

Abstract

Described is a method including a sequence of process steps, Figs. 1A-1D, that permits the fabrication of multilevel metal structures for field-effect transistor (FET) circuitry with submicron line widths.

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Submicron FET Process Step Sequence to Provide Multilayer Metal Structure

Described is a method including a sequence of process steps, Figs. 1A-1D, that permits the fabrication of multilevel metal structures for field-effect transistor (FET) circuitry with submicron line widths.

The process guarantees a planar surface topography for the corresponding submicron metal line width structure, in a way which makes these kinds of metal line width structures in a SiO(2) insulator environment with electrically acceptable aspect ratios, (e.g., line width: line thickness = 2:^) possible at all. For example, with a 1/2 Mu metal line width structure, the method avoids hot planarization steps like growing thermal oxide after polysilicon.

The last hot process step (Fig. 1D) is a hot CVD SiO(2) step, which is also used to drive the before implanted N+ diffusion pockets a little under the polygate. This is done to avoid the existence of resistances in series to the channel.

The basic two methods to obtain a planar structure are SiO(2) resputtering and via hole refill with metal. The protection of the floating gates is performed before 1. metal, by not totally removing the CVD - SiO(2) layer over the polygate during the resputtering step, Fig. 2A.

The via holes to the heavily implanted source and drain regions and to the polygate are etched chemically. Via holes to source and drain should be preetched with reactive ion etching to reduce the flaring. Then in a series of steps, the...