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# Method of Testing for Shorts

IP.com Disclosure Number: IPCOM000085147D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 22K

IBM

Roth, JP: AUTHOR

## Abstract

The following method determines whether shorts are testable or not. If testable, the D-algorithm [1] is extended to compute a test therefor.

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Method of Testing for Shorts

The following method determines whether shorts are testable or not. If testable, the D-algorithm [1] is extended to compute a test therefor.

Assume with no loss of generality that the logic being tested is logically organized according to levels either for primary outputs or primary inputs. First, assume primary inputs. Shorts between the interconnecting lines may introduce feedback. If they do not introduce feedback, there is no difficulty in generating a test for them. If they do, a simple test determines whether or not such a short failure is testable.

Theorem: If the number of inversions between the two points of the short in the correct circuit is even then the failure is untestable; if odd then it is testable.

Proof: First, dispose of the case where the number of circuits between the two points of the short is odd. In this case, as may be seen by examination of simple cases, the application of a constant signal which imposes a 1 on a particular line will exhibit an alternating signal of 1010 etc., which behavior is simple to detect. A test then would be simply an output which causes this alternating behavior to occur and propagate to the primary output. If it were not propagatable by, for example, the D-algorithm, then the failure would not exhibit detectable incorrect behavior and would not cause an error in the logic.

On the other hand, assume that an even number of inversions occur between the two points of shorting. Then, as is well known, an appropriate pattern may set up a latch within this loop. In some technologies, for instance the bipolar, the short is an AND of the two wires that it connects. In this case, as shown in the figure a 0 in the loop obtained from the previous computation would give the incorrect signal, namely, a 0 for all inputs u of the line connecting it regardless of the value of u. This would be an error which could be propagated to the primary output. This completes the discussion of the recognition of untestable shorts.

The D-algorithm has been extended to cover the case where the failure is a short which does not introduce feedback. In this case, the generation of the test by driving a D-chain [1] from the point of failure to a primary output and then following that by the CONSISTENCY [1] algorithm, which obtains primary input signals consistent with those assigned to some of the logic lines in the D-drive,
[1] is extended in the following way. If a short occurs, in any bipolar technology, then the short becomes the AND of the connections. Thes...