Browse Prior Art Database

Encoding Decoding for Magnetic Record Storage Apparatus

IP.com Disclosure Number: IPCOM000085165D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Kiwimagi, RG: AUTHOR

Abstract

AC-coupled recording/readback channel causes signal distortion in a signal having a net DC component. Accordingly, it is desirable to provide data in an encoded form which contains no DC, yet achieves high-recording efficiencies for enhancing data recording densities on magnetic record storage media.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 3

Encoding Decoding for Magnetic Record Storage Apparatus

AC-coupled recording/readback channel causes signal distortion in a signal having a net DC component. Accordingly, it is desirable to provide data in an encoded form which contains no DC, yet achieves high-recording efficiencies for enhancing data recording densities on magnetic record storage media.

Shown is a (d, k) code, wherein d=0 and k=0. The code has a digital sum variation (DSV) of nine bit periods. Such coding, generally, is taught by P. A. Franaszek, "Sequence-State Method for Run-Length-Limited Coding", IBM Journal of Research and Development, July 1970. The 4-to-5 translation is provided by a two-stage encoder/decoder. The two-stage encoder operation is varied by the accumulated digital sum (DS) such that the DSV of the encoded signal sequence is limited to nine.

The code has states 1-5 as shown in the state diagram. The state transitions are labeled -4, -3, -2, -1, 0, +1, and +2 corresponding to the digital sum of the code words which produce the respective state transitions.

The tables below give the four-bit encoder inputs, the five-bit encoder outputs which depend on the system state, and the digital sum of the output code words.

Encoder Input Encoder Output States 1-5 DS

0 1 0 0 0 0 1 0 0 0

1 1 1 0 0 1 1 1 0 0

1 0 1 1 0 1 0 1 1 0

1 0 1 0 1 1 0 1 0 0

1 1 1 1 1 1 1 1 1 0

0 1 0 1 1 0 1 0 1 0

State 1 DS States 2-5 DS

0 0 0 0 1 0 0 0 0 -4 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 -3 0 0 1 0 1 1 1 0 0 0 0 1 0 0 0 -2 0 1 0 1 0 1 1 1 0 0 1 1 1 0 0 -2 1 1 1 1 0 1 0 1 1 0 1 0 1 1 0 -2 1 0 1 0 0 1 0 0 1 1 1 0 0 1 1 -2 1 1 0 1 1 1 States 1-4 DS State 5 DS 0 0 1 0 1 0 0 1 0 -1 0 0 0 1 0 2 0 1 1 1 1 0 1 1 1 -1 0 0 1 1 1 2 1 1 0 1 1 1 1 0 1 -1 0 1 1 0 1 2 1 0 0 1 0 1 0 0 1 -1 1 1 0 0 1 2.

An efficient hardware arrangement for achieving the above truth tables is shown in the drawing. The binary data input is first encoded to an eight-bit unit in a first encoder. The second encoder follows the first encoder and converts the eight bits to five bits, which is the runlength limited balanced encoded sequence of data which is biased in accordance with the sequence DS decoder circuit sums S1 and S2.

1

Page 2 of 3

Decoding is straightforward in that a first decoder takes...