Browse Prior Art Database

Two Level Data Shifting System

IP.com Disclosure Number: IPCOM000085188D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 8 page(s) / 141K

Publishing Venue

IBM

Related People

Shimp, EM: AUTHOR [+2]

Abstract

A two-level data shifting system is described, wherein one level shifts by byte size increments and the other level shifts by bit size increments. Both levels include circuitry for inserting pad bits for those bits shifted out if padding is explicitly called for. The shifting circuitry described herein minimizes the number of data input and data output connections needed at the bit shift level. This is particularly advantageous when implementing the system by means of LSI (large-scale integration) technology.

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Two Level Data Shifting System

A two-level data shifting system is described, wherein one level shifts by byte size increments and the other level shifts by bit size increments. Both levels include circuitry for inserting pad bits for those bits shifted out if padding is explicitly called for. The shifting circuitry described herein minimizes the number of data input and data output connections needed at the bit shift level. This is particularly advantageous when implementing the system by means of LSI (large-scale integration) technology.

Most Instruction Processing Units (IPU's) have a required function of shifting and formatting data and thus require some shift hardware. It is not uncommon for data widths to be in the range of 8 bytes, 16 bytes, or larger. For sake of example, the requirement to shift a data bus having a width of 8 bytes (a total of 64 data bits and 8 parity bits) any number of bit positions from 0 to 63 in either a right or left direction is assumed herein.

To a logic designer, LSI technology at the chip level usually appears to be I/O limited. That is, there never seems to be enough chip I/O's available to support the logical function which can be implemented with the number of circuits available on the chip. The trick is then to design the logical function in a manner that minimizes chip I/O usage, which normally results in minimizing the number of chips needed to perform the function. The shifting scheme described herein minimizes chip I/O requirements and results in a net savings of chips needed to implement the function (without a net decrease in performance).

The shifter and shifter controls generation described herein are similar to those described in our U. S. Patent No. 3,916,388, entitled "Shifting Apparatus for Automatic Data Alignment". Additions to the shifter and shifter controls of such patent are made in order to fulfill the requirement of shifting to a bit level.

The shifter described in the patent shifts only to the byte level and is described as being used to align data to the byte level, in data transfers of 8 bytes between memory and the IPU. The shifter described herein provides the same alignment function, but in addition will also provide for internal shifts of data (data internal to the IPU) to the bit level.

To accomplish this, a shifting system as shown in Fig. 1 is used wherein the overall shifter is shown comprised of a byte level shifter and a bit level shifter. As the name implies, the byte level shifter shifts data right or left a given number of bytes. Also at this level, pad bytes can be inserted for those bytes shifted out if padding is explicitly called for. The pad byte bits can be either all 0's, all 1's, the sign bit of the input field or any one byte of the input field. This padding will be touched on to some extent later. The output of the byte level shifter feeds the bit level shifter and also is outputted to memory via the Storage Data Bus In (SDBI) of Fig. 1. The bit...