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Comparator with Adaptive Minimum Threshold

IP.com Disclosure Number: IPCOM000085198D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Crow, SS: AUTHOR

Abstract

Circuit 1, Fig. 1, provides an adaptive threshold control signal B for minimum threshold comparator 2. The latter in turn provides an enabling signal for signal processor 3. The system prevents false data bit decodes.

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Comparator with Adaptive Minimum Threshold

Circuit 1, Fig. 1, provides an adaptive threshold control signal B for minimum threshold comparator 2. The latter in turn provides an enabling signal for signal processor 3. The system prevents false data bit decodes.

Processor 3 is part of an on/off keyed (OOK) pulse digital radar frequency data link system. Its AND gate 4, when enabled by comparator 2, gates the output signal of a 3db leading edge detector circuit 5 to pulse width shaper circuit
6. The input of circuit 5 is connected to terminal 7 to which is applied the incoming video signal A from the IF stage of the system receiver, not shown. The output of circuit 6 is fed via terminal 8 to a general or special purpose computer CPU, not shown, for further processing. Control signals RESET, CLOCK and ENABLE are provided by the CPU in turn.

Adaptive minimum threshold (AMT) circuit 1 analyzes signal A and the output signal C of processor 3. Signal A is compared by comparator 9 with a feedback signal FB derived from signal B via voltage divider network 10, 11. The output of comparator 9 is decoded by logic 12 to determine if the incoming pulse width exceeds the predetermined expected data link standard. To determine this condition, in response to a rise in the output voltage of comparator 9, logic 12 provides countup pulses CU derived from a high-frequency pulse signal CLOCK provided by the CPU.

Pulses CU increment the UP/DOWN counter of stage I of block 16 in the forward direction. In response to a drop in the output voltage of comparator 9, logic 12 provides countdown pulses CD which decrement the counter. Logic 12 in response to changes in the signal level of comparator 9 also provides a conditioning signal GT to the pulse width analyzer 13. In turn, analyzer 13 provides a control signal TM via NAND gate 14 to logic 12 whenever the duration, i.e., width, of incoming signal A is in excess of the standard thereby disabling the counter stage I.

Logic II of stage II decodes the output signals of counter stage I and provides complementary overflow and underflow conditioning signals OF, UF, respectively, to logic 12. D/A converter stage III converts the complementary digital output signa...