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Error Correction Code Syndrome Transposition

IP.com Disclosure Number: IPCOM000085201D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Sliz, NB: AUTHOR

Abstract

Many computer systems use error correction codes (ECC's) which increase memory reliability. The increase in reliability often results in a decrease in performance because of the requirement that the data be checked and if necessary, corrected by the receiving unit before the receiving unit proceeds in the normal processing of the data. It is desirable to reduce the "inline" ECC check and correct time by overlapping it with normal processing of the data.

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Error Correction Code Syndrome Transposition

Many computer systems use error correction codes (ECC's) which increase memory reliability. The increase in reliability often results in a decrease in performance because of the requirement that the data be checked and if necessary, corrected by the receiving unit before the receiving unit proceeds in the normal processing of the data. It is desirable to reduce the "inline" ECC check and correct time by overlapping it with normal processing of the data.

The ECC check lines (flip bit lines) are positional in nature with respect to the input data. If the data is processed (altered or transposed in some way) before it is corrected, the original positional nature of the correction lines with respect to the data is either lost entirely or may be difficult and costly to reconstruct.

The technique described here allows for some processing of the data overlapped with the necessary ECC check function. The flip bit lines are transposed such that they are positional again with the processed data. This results in being able to correct the input data after it has been processed giving a net increase in operational performance.

The time taken to align data (normal processing time) is overlapped with the time used for doing the ECC check on the data, such that a reduction in the overall time necessary to perform all functions is accomplished.

As shown in Fig. 1, the ECC correct function is performed by circuit 10 on data that is the output of the byte level shifter 12, which is aligning the data from store 14. The increase in hardware necessary for this technique is minimal. There exists only one path for data from store 14 to the data flow 15 (the dashed line from the ECC check block 20 to the ECC correct block 10 represents syndrome bits, not data), hence, the need to control cycle timing does not exist. The overall processing time for the data has been reduced by T1 if T3 is greater than T1 or by T3 if T1 is greater than T3, since these times are overlapped.

The basis for being able to perform the ECC correct function on the output of the byte level shifter 12 with a minimum hardware impact is the particular SEC- DED (single-bit error correct, double-bit error detect) code that is used (see Fig.
2). Because a byte level shift is actually being done on store 14 data by the data aligner 12, a data bit on the output of the aligner can appear in any of eight data bit slots with respect to the input data slot that is occupied. The bit slot that it appears in is a function of the shift direction and the byte shift amount.

To illustrate this condition, a table of where byte 2, bit 18 (refer to Fig. 2) would appear on the output of the aligner 12 as a function of byte shift amount and direction is shown. Data Bit Slot On Shift Direction Byte Shift Amt. Data Bit Slot On Input To Aligner Output of Aligner Byte 2, Bit 18 Right 0 Byte 2, Bit 18 Byte 2, Bit 18 Right 1 Byte 3, Bit 26 Byte 2, Bit 18 Right 2 Byte...