Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Silicon Memory Cube

IP.com Disclosure Number: IPCOM000085217D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Kolankowsky, E: AUTHOR [+2]

Abstract

This silicon memory cube includes high-density, field-effect transistor (FET) array chips stacked upon each other and superimposed on a bipolar control chip. The silicon memory cube includes interconnection structure, not shown, for interconnecting the FET memory chips to the bipolar control chip.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Silicon Memory Cube

This silicon memory cube includes high-density, field-effect transistor (FET) array chips stacked upon each other and superimposed on a bipolar control chip. The silicon memory cube includes interconnection structure, not shown, for interconnecting the FET memory chips to the bipolar control chip.

The performance of each FET array chip is improved by a factor of n, where n is equal to the number of FET chips stacked. (e.g., if the FET cycle time is 50 ns, the described logical design operates at 10 ns assuming 5 FET chips are stacked.)

In addition, the logic of the silicon memory cube is designed to accept data at a rate equal to a clock frequency of the source. Many sources may be placed in parallel bus arrangements as long as their individual clock frequencies are brought into the silicon memory cube.

The FET's have low-power dissipation. The bipolar chip, at the bottom (or top) of the stack, provides the high performance and control functions.

The figures are briefly described as follows: FIG. 1-SYSTEM DATA FLOW:.

This figure shows the block diagram of the system. The main components are the chip selector, address distributor, control and timing pulse generator (TPC) and the five array chips. FIG. 2-CHIP SELECTOR:.

The chip selector includes a five-bit shift register. The shift register can be initialized by the reset pulse during the zero address mode, to select chip 1 state, or by the contents of the address bus during the random-access mode (to select chip 1, 2... or 5 state). The chip selector is shifted one position by the chip advance pulse. FIG. 3-ADDRESS DISTRIBUTOR:.

The address distributor includes a ten-bit binary counter. The counter can be initialized by the reset pulse during the zero address mode, to address 0, or to any random address as received on the address bus during the random-access mode. The binary counter can be incremented by 1 each time the address advance pulse is applied. FIG. 4-ARRAY CHIP:.

The array chip contains a 1024 x 9 array of cells, the bit drive and bit sense system, a 9-bit data-in and a 9-bit data-out register. The addresses received from the address distributor are decoded in the address decoder.

The silicon memory not only accents the density factor, but also further enhances performance by minimizing line lengths for interconnections. A logical description of the operation follows: A. MODE OF OPERATION:

1. ZERO ADDRESS MODE - Read or write operations are

executed starting with address zero....