Browse Prior Art Database

Decoder Clamp for Limiting Word Line Excursion

IP.com Disclosure Number: IPCOM000085218D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Dennison, RT: AUTHOR [+4]

Abstract

Described is a means of minimizing the effect of integrated component tolerances on the voltage levels of a Read/Write array word line. The advantages of word line level control are primarily memory-cell stability.

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Decoder Clamp for Limiting Word Line Excursion

Described is a means of minimizing the effect of integrated component tolerances on the voltage levels of a Read/Write array word line. The advantages of word line level control are primarily memory-cell stability.

Specifically, this approach compensates for power supply tolerance, transistor Beta and VBE, and Schottky diode VF. In the drawing, a typical word address path including the true/complement-state driver, decoder, and memory word-line driver is illustrated. The means of clamping, enclosed within the broken line, comprises transistors T3, T4, T5, Schottky barrier diodes S2, S3, and resistors R3 and R4.

A downlevel (VBD) at node B corresponding to an unselected word line is primarily determined as: VBD = VR + VBE (TA) - VF (SA) + VBE (T1) - VF (S1)
(1).

Without the subject clamp the uplevel (VBU) at node B corresponding to a selected word line is primarily determined as: VBU = -IB (T2) ù R2 (2).

With the addition of this clamp, the selected level at node B may be made essentially independent of the base current variation IB (T2). VBU = VR +VBE (T5) - VF (S3) +VBE (T4) - VF (S2) +VBE (T3)
(3).

By designing for the following equalities, the voltage swing at node B, VBU-VBD, will become only a function of VBE (T3). The equalities are reasonably satisfied by the tracking of the characteristics of devices proximally integrated in a semiconductor chip. VBE (TA) = VBE (T5)

VF (SA) = VF (S3)

VBE (T1) = VBE (T4)

VF (S...