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Current Switch Read Only Programmable Logic Array

IP.com Disclosure Number: IPCOM000085219D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 5 page(s) / 144K

Publishing Venue

IBM

Related People

Cavaliere, JR: AUTHOR [+3]

Abstract

One of the objectives in designing a programmable logic array (PLA) structure is to achieve a fast access time through the several elements thereof, i.e., inputs decoders, AND (SEARCH) array, OR (OUTPUT) array, and latch outputs. Access is enhanced by employing high-speed circuits, such as CSEF, (current-switch emitter-follower) and using a minimum number of levels thereof.

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Current Switch Read Only Programmable Logic Array

One of the objectives in designing a programmable logic array (PLA) structure is to achieve a fast access time through the several elements thereof,
i.e., inputs decoders, AND (SEARCH) array, OR (OUTPUT) array, and latch outputs. Access is enhanced by employing high-speed circuits, such as CSEF, (current-switch emitter-follower) and using a minimum number of levels thereof.

Fig. 1 shows known CSEF circuitry implementing the minimum elements of a PLA, i.e., inputs, phase splitters, AND array, OR array and outputs. A CSEF phase splitter LA accepts an input 1B and produces both polarities of the input signal 1C and 1D. When input 1B is ON, outputs 1C and 1D are OFF and ON, respectively. When input 1B is OFF, outputs 1C and 1D are ON and OFF, respectively.

The AND array 1E comprises a transistor array driven by phase splitter outputs 1C and 1D. Each phase splitter output controls the bases of a column of transistors. The personality of the AND array is programmed by connecting or not connecting the emitters (programmable connections 10) to the corresponding output lines. An output line then, represents the OR of the phase splitter inputs to the transistors whose emitters are connected. (The term AND array is generic and refers to the first of two arrays of a PLA. It is here implemented as OR's followed by inverts.)

The columns of transistors in the AND array may also be considered as an added level of emitter-followers, each column being an emitter-follower, with a multiplicity of emitters which are optionally OR'ed into a row output 1F.

The output lines of the AND array are inverted by CSEF inverters 1G, whose outputs 1H drive rows of transistors of the OR array 1I. The personality of the OR array is programmed by connecting or not connecting the emitters programmable connections 11 of the rows of transistors to the corresponding output line 1J. An output line 1J, then represents the OR of the inverter signals 1H that enter the connected transistors. A column of transistors of the OR array together with the associated circuitry comprise a multiinput CSEF, 1K, with an in- phase output 1L.

When decoders instead of simple phase splitters are to be interposed in Fig. 1 between the inputs 1B to the PLA and the AND array 1E, the added logic lengthens the delay time through the PLA. Similarly, delay time is increased wh...